DocumentCode :
956591
Title :
A Novel Single Polysilicon EEPROM Cell With a Polyfinger Capacitor
Author :
Na, Kee-Yeol ; Kim, Young-Sik ; Kim, Yeong-Seuk
Author_Institution :
IHP Microelectron. GmbH, Frankfurt
Volume :
28
Issue :
11
fYear :
2007
Firstpage :
1047
Lastpage :
1049
Abstract :
In this letter, we describe a novel single polysilicon electrically erasable read-only memory cell with polyfinger capacitor for the control gate (CG). A finger-type capacitor structure with CoSi2 is applied to a floating gate and the CG of the proposed cell. The proposed cell is fabricated by using a 0.18-mum standard logic process. The intergate dielectrics of the proposed cell are formed by a conventional lightly doped drain spacer material that is composed of SiO2 and Si3N4 to avoid any process modification. A Fowler-Nordheim tunneling method is applied for the programming and erasing of the cell. Endurance characteristics of up to 120 000 cycles are demonstrated. The proposed cell shows acceptable data retention characteristics.
Keywords :
EPROM; capacitors; elemental semiconductors; random-access storage; silicon; CoSi2 - Binary; Fowler-Nordheim tunneling method; Si3N4 - Binary; SiO2 - Binary; cell erasing; cell programming; control gate; finger-type capacitor structure; floating gate; intergate dielectrics; lightly doped drain spacer material; nonvolatile memory; polyfinger capacitor; polysilicon EEPROM cell; polysilicon electrically erasable read-only memory cell; size 0.18 mum; standard logic process; CMOS logic circuits; Capacitance; Capacitors; Character generation; Dielectrics; EPROM; Logic devices; Logic programming; Nonvolatile memory; Tunneling; Fowler–Nordheim tunneling (FNT); nonvolatile memory (NVM); polyfinger capacitor; single polysilicon electrically erasable read-only memory (EEPROM); standard logic process;
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/LED.2007.908498
Filename :
4367561
Link To Document :
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