Optimizing gettering conditions for VLSI chips using simple yield model

Conditions of an effective gettering procedure for VLSI processing are investigated by means of analytical simulation. The effectiveness of a gettering procedure is judged from the VLSI yield when the density of heavy metal impurities and gettering capability are varied over a wide range. It is found that the VLSI yield is seriously degraded by the negative effects of gettering, namely, wafer warpage and dislocation propagation from a gettering site region to a device area. It is seen that gettering effects are profitable in VLSI processes only when the density of heavy metal impurity to be removed is not too high