DocumentCode
958867
Title
Chip Carrier Packaging Applications
Author
Bauer, John A.
Author_Institution
Radio corp of America,Moorestown, NJ
Volume
3
Issue
1
fYear
1980
fDate
3/1/1980 12:00:00 AM
Firstpage
120
Lastpage
125
Abstract
The increasing number of pins required by large-scale integrated (LSI) devices has brought a corresponding increase in the size of dual in-line and flatpack packages using standard 0.1 in printed circuit board interconnects. The chip carrier approach, as originally applied on ceramic beards in place of hybrids and currently being introduced for epoxy/glass boards, offers significant packaging improvement. Characteristics, advantages, and comparisons are shown for both types.
Keywords
Integrated circuit packaging; Assembly; Ceramics; Circuit faults; Circuit testing; Electronics packaging; Electrons; Integrated circuit interconnections; Pins; Printed circuits; Space technology;
fLanguage
English
Journal_Title
Components, Hybrids, and Manufacturing Technology, IEEE Transactions on
Publisher
ieee
ISSN
0148-6411
Type
jour
DOI
10.1109/TCHMT.1980.1135592
Filename
1135592
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