Long-term testing of 68 kbit bubble device chips

Long-term testing of the data reliability has been done on 68 kbit bubble device chips of a serial shift register design. The chips were fabricated using LPE garnet of the YSmLuGeCa composition with 3 micron strip-width. The bubble propagation structure contained a single permalloy element per 16 micron period. Testing was done at 50 kHz and 40 Oe rotating field over a chip temperature range from 30°C to 100°C. The data show that such chips have at least 15 Oe of bias field margin with an error probability of less than per bubble per cycle of rotating field, although this margin can be reduced by chip defects. Preliminary results indicate that the operating parameters of the chip have a significant impact on the error rate. An investigation of bubble propagation, separated out from the other bubble functions, shows that the propagation error rate near the high bias field limit decreases more rapidly than exponentially with decreasing bias field.