A high speed and low power on CMOS/SOI technology

Author

Lee, Minhung ; Fujishima, Minoru ; Asada, Kunihiro

Author_Institution

Dept. of Electron Eng., Tokyo Univ.

Volume

40

Issue

11

fYear

1993

fDate

11/1/1993 12:00:00 AM

Firstpage

2103

Lastpage

2104

Abstract

Summary form only given. The propagation delay times were improved up to two times in deep-submicron CMOS/SIMOX ring oscillators by reducing the poly-Si gate thickness (t_m). The measured power dissipations with 0.1- to 0.25-μm gate length are under 1.5 fJ, while theoretical minimum power dissipations can be reduced down to 0.1 fJ for 0.15-μm gate length at a supply voltage of 1.5 V. SOI technology shows promise for high speed and low power by reducing the gate fringing capacitance which is correlated to t_m

Keywords

CMOS integrated circuits; SIMOX; capacitance; delays; integrated circuit technology; 0.1 to 0.25 micron; 1.5 V; CMOS/SOI technology; Si; deep-submicron CMOS/SIMOX ring oscillators; gate fringing capacitance; gate length; high speed; low power; poly-Si gate thickness; power dissipations; propagation delay times; supply voltage; CMOS technology; Capacitance; Charge carrier processes; Circuit simulation; Electrons; Monte Carlo methods; Power dissipation; Propagation delay; Quantization; Thickness control;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.239769

Filename

239769