Development of polysilicon TFTs for 16 MB SRAMs and beyond

Author

Batra, Shalini ; Maddox, R. ; Tran, L. ; Manning, Monte ; Dennison, C. ; Fazan, P.

Author_Institution

Micron Semicond. Inc., Boise, ID

Volume

40

Issue

11

fYear

1993

fDate

11/1/1993 12:00:00 AM

Firstpage

2125

Lastpage

2126

Abstract

Summary form only given. The authors discuss the development and optimization of polysilicon grain microstructure, gate dielectric ,and light doped drain offset (LDO) for thin-film transistors (TFTs). The nominal TFTs used in this study had a W/L of 0.7/1.2 μm with a drain offset of 0.3 μm. Different gate dielectrics (SiO ₂, NO, ONO) with thickness of 10-50 nm were evaluated. The results suggest that an LDO implant is essential for obtaining ON/OFF ratios greater than 10⁵ while reducing the TFT sensitivity to drain-offset misalignment. The ONO dielectric is superior to NO stacks or oxide in terms of oxide leakage and ON/OFF ratios. A 3×10¹⁴ Si implant after solid-phase crystallization (SPC) improves the slope by reducing the interface trap density. Therefore, significant performance enhancements in leakage (<50 fA) and ON/OFF (>10⁶) can be realized using LDO TFTs with stacked gates and an Si implant following SPC

Keywords

MOS integrated circuits; SRAM chips; electron traps; interface electron states; ion implantation; thin film transistors; 16 MB SRAMs; LDO implant; NO stacks; ON/OFF ratios; ONO dielectric; drain offset; gate dielectric; interface trap density; light doped drain offset; polysilicon TFTs; polysilicon grain microstructure; solid-phase crystallization; thin-film transistors; Conductors; Degradation; Design for quality; Dielectrics; Grain size; Implants; Microstructure; Random access memory; Stability; Thin film transistors;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.239803

Filename

239803