A 3D sidewall flash EPROM cell and memory array

Summary form only given. A promising new sidewall flash EPROM (electrically programmable read-only memory) cell has been implemented in a novel memory array to demonstrate the potential of this cell for shrinking future generations of ultrahigh-density, high-performance flash EPROM arrays. The sidewall flash EPROM cell is a 3-D, single transistor, floating gate memory cell that is fabricated on the sidewalls of a narrow silicon pillar. Current flows vertically along the sidewalls of the pillar from the top of the pillar (drain), to the base of the pillar (source). Because both the source and the word lines lie buried beneath the surface of the wafer, the sidewall EPROM realizes extremely small cell size, approaching the theoretical minimum cell size dictated by the lithography dependent pitch. The sidewall EPROM cell becomes increasingly attractive as EPROM scaling continues down into the deep submicron regime. This is because the channel length of the memory transistor remains the same as geometries are scaled and only the width decreases. Another significant advantage is that isolation between cells is inherent in this approach and is not a concern when scaling