DocumentCode
960433
Title
High voltage implanted RESURF p-LDMOS using BiCMOS technology
Author
Van Calster, A. ; Witters, J.
Volume
40
Issue
11
fYear
1993
fDate
11/1/1993 12:00:00 AM
Firstpage
2132
Abstract
Summary form only given. The authors present a complementary RESURF p-LDMOS in which the n+ buried layer is used as an effective substrate and a field implant is introduced to modify the drift charges. The implant conditions in this case, particularly the placements, are studied. After processing, V B are investigated with different implant placement (L A, L B) and field oxide lengths L F. It is found that although the ion implant covers part of the drift region, the device performance can still be greatly improved. Results show that a long enough implant, compatible with L F, under the field oxide can result in the maximum, V B= V BP. This is verified by simulation results, which show that the peak of the surface electric field is significantly reduced. Results also show that a full length (L F) implantation under the field oxide can result in the minimum R on for a fixed L F
Keywords
BiCMOS integrated circuits; integrated circuit technology; ion implantation; complementary RESURF p-LDMOS; device performance; drift charges; field implant; field oxide lengths; implant conditions; n+ buried layer; surface electric field; Application specific integrated circuits; BiCMOS integrated circuits; Boron; Implants; Impurities; Information systems; Voltage;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/16.239814
Filename
239814
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