Ultralow on-resistance p-channel lateral DMOS fabricated on (110)-oriented Si substrate

Summary form only given. A p-channel lateral DMOS (LDMOS) featuring improved on-resistance through the use of a (110)-oriented Si substrate is presented. The authors fabricated p-channel LDMOS on both (100) and (110) substrates and compared their on-resistance. The on-resistance of the samples was determined as a function of their effective longitudinal gate field, E_inv. The measured threshold and breakdown voltages were -3.28 and -51 V for the (110) sample and -2.54 and -46 V for the (100) sample. When E _inv was -5 MV/cm, the measured specific on-resistance of the (110) sample was 2.27 Ω-cm², only 0.64 times as much as the 3.52 Ω-cm² measured for the (100) sample. It was found that the on-resistance ratio between the p-channel LDMOS fabricated on the (110) and (100) substrates can be reduced by increasing E_inv