Yield implications and scaling laws for submicrometer devices

Author

Ferris-Prabhu, Albert V.

Author_Institution

IBM Gen. Technol. Div., Essex Junction, VT, USA

Volume

1

Issue

2

fYear

1988

fDate

5/1/1988 12:00:00 AM

Firstpage

49

Lastpage

61

Abstract

Yield scaling laws are developed that are applicable to VLSI (very large-scale integration) devices with features of minimum dimension smaller than that at which the defect-size probability density function peaks. Expressions for the fault-probability kernel of reduced-size devices are derived in terms of the full-size or prototype device. The role of the defect-size probability density function with respect to the average fault probability is explained and expressions for it are developed. The ensuing scaling laws are utilized to obtain expressions for the expected number of faults, and then applied to the evaluation of the yield for several different cases. The implications of the results for yield and productivity are examined

Keywords

VLSI; integrated circuit technology; probability; VLSI; average fault probability; defect-size probability density function; fault-probability kernel; monolithic IC; scaling laws; submicrometer devices; Density functional theory; Information geometry; Instruments; Poisson equations; Predictive models; Probability density function; Productivity; Shape; Very large scale integration; Yield estimation;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/66.4374

Filename

4374