Device Modeling for Submicron FET Integrated Circuits

Phys!cal understanding of submicron device phenomena is key to the efficient use of these structures in circuit applications and to the invention of new device structures and concepts. Modeling activities are categorized in hierarchical levels of abstraction which extends the concept of hierarchical system simulation down to the fundamental levels of process modeling. Major emphasis in field-effect transistor (FET) modeling beyond the micron dimension is on the incorporation of geometry effects and high field transport on active devices. As geometry sizes shrink, the effects of both carrier types become important even in unipolar devices. For very large-scale integrated (VLSI) circuits at these geometries modeling of parasitic devices like interconnections and isolation are important in determining circuit operation and performance.