• DocumentCode
    962269
  • Title

    A Class of Odd-Weight-Column SEC-DED-SbED Codes for Memory System Applications

  • Author

    Kaneda, Shigeo

  • Author_Institution
    First Research Section, Communication Principles Research Division, Musashino Electrical Communication Laboratory, N. T. T., Midori-cho, Musashino-shi, Tokyo, Japan.
  • Issue
    8
  • fYear
    1984
  • Firstpage
    737
  • Lastpage
    739
  • Abstract
    Error correcting codes are widely used in memory systems to increase reliability. Especially in a memory systern that uses byte-organized memory chips, which each contain b (≫1) output bits, a single chip failure is likely to affect many bits within a byte. Single-bit error correcting-double bit error detecting-single b-bit byte error detecting codes (SEC-DED-SbED codes) are suitable for increasing the reliability of memory system. This correspondence presents a new class of odd-weight-column SEC-DED-SbED codes for b = 4. The code length is 2r-1 - 2[r/2], where r is the number of check bits and [ ] denotes the ceiling or next largest integer. The proposed SEC-DED-S4ED codes are the best-known codes.
  • Keywords
    Circuits; Error correction codes; Matrix converters; Byte-organized memory chips; LSI implementation; error-correcting codes; reliability; single-bit error correcting-double-bit error detecting-single-b-bit byte error detecting codes (SEC-DED-SbED codes);
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.1984.5009359
  • Filename
    5009359