DocumentCode
962813
Title
Some Aspects of the Dynamic Behavior of Hierarchical Memories
Author
Fenwick, Peter M.
Author_Institution
Department of Computer Science, University of Auckland, Auckland, New Zealand.
Issue
6
fYear
1985
fDate
6/1/1985 12:00:00 AM
Firstpage
570
Lastpage
573
Abstract
In a computer system with a cache memory, the cache is effectively empty following a job switch, leading to a low hit rate and consequently lowered performance until the cache becomes reasonably full. The analysis shows that a job must run for several milliseconds before the average performance approaches that expected from a steady-state analysis. Care may therefore be needed in designing memory systems which have very high page-fault rates from main memory, or which include many levels in the memory hierarchy.
Keywords
Cache memory; Cost function; Decoding; Filling; Multiplexing; Performance analysis; Random access memory; Read-write memory; Steady-state; Switches; Bubble memory; cache memory; dynamic behavior; memory hierarchy; performance degradation;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1985.5009413
Filename
5009413
Link To Document