Title :
Performance Analysis of a Multiprocessor-Based Packet Switch in Networks with Link-Level Sliding-Window Flow Control
Author :
Liu, Steven S. ; Chow, Q.C.
Author_Institution :
Telecommunications Research Laboratory, GTE Labs, Waltham, MA 02254.
Abstract :
In the literature, performance studies on packet switches and link-level flow control procedures were treated separately. In this paper, we use a queueing network approach to analyze packet switch performance in terms of the combined effects of switch architectures and link-level flow-control procedures. Results of the study provide us with valuable insights about switch designs and unfold the relationship between switch performance and packet acknowledgment schemes.
Keywords :
Automatic testing; CMOS logic circuits; Circuit faults; Circuit testing; Integrated circuit interconnections; Logic testing; Packet switching; Performance analysis; Switches; Switching circuits; Queueing network analysis; multiprocessor architecture; packet acknowledgment scheme; packet switch; performance analysis; sliding window flow control;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1987.5009547
