Title :
Designing high-performance processors using real address prediction
Author :
Hua, Kien A. ; Liu, Lishing ; Peir, Jih-Kwon
Author_Institution :
Dept. of Comput. Sci., Central Florida Univ., Orlando, FL, USA
fDate :
9/1/1993 12:00:00 AM
Abstract :
The authors propose design techniques that may significantly simplify the cache access path, and hence offer the opportunity of shorter cycle time or fewer pipeline stages. Their proposals are based on highly accurate prediction methods that allow them to efficiently resolve address translation information early in the pipe
Keywords :
buffer storage; pipeline processing; address translation; cache access path; high-performance processors; pipeline stages; prediction methods; real address prediction; shorter cycle time; Application software; Central Processing Unit; Computer architecture; Galois fields; Hazards; Pipeline processing; Prediction methods; Process design; Proposals; Very large scale integration;
Journal_Title :
Computers, IEEE Transactions on
