Test methods for crosstalk-induced delay and glitch faults in network-on-chip interconnects implementing asynchronous communication protocols

Variations in crosstalk is an added source of delay and glitch faults in system on chips built with deep sub-micron technology, especially in chips using wide and long buses. Many of these faults, in such sub-micron chips, may only appear when the chip works at normal operating speed. These crosstalk-induced faults are more serious in systems built with globally asynchronous locally synchronous principles. The authors propose efficient methods for at-speed testing of such faults in asynchronous links connecting, for example, two switches/routers of an network-on-chip communication infrastructure. The proposed delay test method has the property that all faulty chips are identified but some good chips may also be characterised as faulty with a small probability. The authors give an analytical analysis regarding this probability as a function of probability of delay fault and number of applied test instances. A simple and pure digital BIST hardware is also proposed, which is represented at register transfer level to implement the delay test method. A method is also proposed for detecting glitches on control lines in a handshaking-based communication link; thereafter it is shown how the method can be extended for detecting glitch faults on data lines. The proposed test methods for detecting delays and glitches provide a complete scheme for detection of crosstalk-induced faults in links in an on-chip communication infrastructure using asynchronous handshaking communication protocols.