• DocumentCode
    964774
  • Title

    Itanium 2 processor 6M: higher frequency and larger L3 cache

  • Author

    Rusu, Stefan ; Muljono, Harry ; Cherkauer, Brian

  • Author_Institution
    Intel Corp., Santa Clara, CA, USA
  • Volume
    24
  • Issue
    2
  • fYear
    2004
  • Firstpage
    10
  • Lastpage
    18
  • Abstract
    The third-generation Itanium processor targets the high-performance server and workstation market. To do so, the design team sought to provide higher performance through increased frequency and a larger L3 cache. At the same time, we had to limit the power dissipation to fit into the existing platform envelope. These considerations led to what we now call the Itanium 2 processor 6M: the latest generation of Itanium 2, which features a 6-Mbyte, 24-way set-associative on-die L3 cache. The design implements a 2-bundle 64-bit explicitly parallel instruction computing (EPIC) architecture and is fully compatible with previous implementations. Although this processors frequency is 50 percent higher than that of the previous generation, the maximum power dissipation holds flat at 130 W to ensure the platform´s backward compatibility.
  • Keywords
    cache storage; microprocessor chips; parallel architectures; pipeline processing; system buses; Itanium 2 processor; L3 cache; parallel architectures; parallel instruction computing; pipeline processing; power dissipation; system buses; Computer aided instruction; Copper; Dielectrics; Error correction codes; Frequency; Power dissipation; Protection; Registers; Thermal management; Workstations;
  • fLanguage
    English
  • Journal_Title
    Micro, IEEE
  • Publisher
    ieee
  • ISSN
    0272-1732
  • Type

    jour

  • DOI
    10.1109/MM.2004.1289279
  • Filename
    1289279