Wafer-scale optimization using computational availability

Author

Landis, David L. ; Nigam, Nitin ; Yoder, Joseph W.

Author_Institution

Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA

Volume

25

Issue

4

fYear

1992

fDate

4/1/1992 12:00:00 AM

Firstpage

66

Lastpage

71

Abstract

It is shown that, given the ability to restructure wafer-level designs, there are different ways to employ redundancy. Redundancy is evaluated by estimating system computational availability over a mission lifetime. This technique is illustrated using two wafer-scale integration (WSI) case studies. The first is a very-fine-grained programmable systolic data processor (PSDP) that contains 4- and 8-b paths, RAM, and control optimized for signal and data processing applications. The second, the Mosaic multicomputer architecture, is a less fine-grained homogeneous architecture in which each node contains a 16-b microprocessor and associated RAM and ROM. Potential benefits of implementing these parallel processing architectures in wafer scale are discussed.<>

Keywords

VLSI; microprocessor chips; parallel architectures; redundancy; Mosaic multicomputer; computational availability; parallel processing architectures; programmable systolic data processor; redundancy; wafer-level designs; Computer architecture; Degradation; Design methodology; Fault tolerant systems; Integrated circuit yield; Power system reliability; Read-write memory; Redundancy; Tiles; Very large scale integration;

fLanguage

English

Journal_Title

Computer

Publisher

ieee

ISSN

0018-9162

Type

jour

DOI

10.1109/2.129051

Filename

129051