A 1.5 mW 68 dB SNDR 80 Ms/s 2 $\times$ Interleaved Pipelined SAR ADC in 28 nm CMOS

This paper presents a power-efficient 80 MS/s, 11 bit ENOB ADC. It is realized in 28 nm CMOS and is based on two interleaved pipelined SAR ADCs. It includes an on-chip reference generator and does not require any external components. The total power dissipation is 1.5 mW, resulting in a low-frequency Walden FOM of 9.1 fJ/conv-step and a low-frequency Schreier FOM of 172.2 dB, which is the largest FOM reported to date for sampling frequencies larger than 1 MS/s. The key aspects in achieving this excellent power efficiency include the choice of ADC architecture, integrator-based amplifiers used for noise filtering, the finite settling of the reference voltage during the SAR conversion, and the modified DAC switching scheme to reduce the DAC switching energy.