Title :
0.9-V DSP blocks: a 15-ns 4-k SRAM and a 45-ns 16-b multiply/accumulator
Author :
Hallmark, Jerry ; Shurboff, Carl ; Ooms, Bill ; Lucero, Rudy ; Abrokwah, Jon ; Huang, Jenn-Hwa
Author_Institution :
Phoenix Corp. Res. Lab., Motorola Inc., Tempe, AZ, USA
fDate :
10/1/1995 12:00:00 AM
Abstract :
4-k SRAM and 16-b multiply/accumulate DSP blocks have been designed and fabricated in complementary heterostructure GaAs. Both circuits operate from 1.5 V to below 0.9 V. The SRAM uses 28,272 transistors in an area of 2.44 mm2. Cell size is 278 μm 2 at 1.0-μm gate length. Measured results show an access delay of 5.3 ns at 1.5 V and 15.0 ns at 0.9 V. At 0.9 V, the power dissipated is 0.36 mW. The CGaAs multiplier uses a 16-b modified Booth architecture with a 3-way 40-b accumulator. The multiplier uses 11,200 transistors in an area of 1.23 mm2. Measured delay is 19.0 ns at 1.5 V and 44.7 ns at 0.9 V. At 0.9 V, current is less than 0.4 mA
Keywords :
III-V semiconductors; SRAM chips; digital arithmetic; field effect logic circuits; field effect memory circuits; gallium arsenide; multiplying circuits; 0.36 mW; 0.4 mA; 0.9 to 1.5 V; 1 micron; 16 bit; 4 kbit; 40 bit; 5.3 to 44.7 ns; DSP blocks; GaAs; SRAM; complementary heterostructure GaAs; modified Booth architecture; multiply/accumulator; Circuits; Clocks; Decoding; Delay; Digital signal processing; Gallium arsenide; Implants; Logic design; Low voltage; Random access memory;
Journal_Title :
Solid-State Circuits, IEEE Journal of
