Electrical Characterization of Packages for High-Speed Integrated Circuits

Advances in silicon bipolar and GaAs FET technology have enabled digital circuits of medium complexity to be fabricated for operation at gigabit rates. However, signal degradation caused by the packaging of these new devices will limit their useful application. A theoretical model to help assess this problem is discussed, and its predictions are compared with results from time domain reflectometry (TDR) and network analysis measurements. Also described is a novel exlension of the TDR technique based on the use of fast Fourier transform (FFT) analysis, including the design of test fixtures and the analysis software which is run on a desktop computer. The results presented demonstrate that both the model and the FFT measurement technique accurately represent the electrical performance of all those packages tested.