The Effect of Joint Design on the Thermal Fatigue Life of Leadless Chip Carrier Solder Joints

The influence of solder joint shape on the reliability of solder joints formed between 84 I/O, 0.025-in (0.635-mm) pitch noncastellated leadless ceramic chip carriers and multilayer printed wiring boards has been quantified. (A castellation is a metallized radial feature on the edge of a ceramic chip carrier for interconnecting conducting surfaces or planes within or on the chip carrier. Castellations are usually on all four edges of the chip carrier. Noncastellated chip carriers may use vias instead of castellations for achieving the same interconnection.) The method is discussed by which a solder joint can be shaped to provide a substantial improvement in thermal cycle performance. Aspects of the investigation that are reported include the room temperature tensile test characterization of the stress/strain behavior of 60Sn/40Pb solder, finite element method calculations of the impact of joint shape on the deformation behavior of leadless ceramic chip carrier solder joints, mechanical shear test characterization of selected solder joint shapes, and thermal cycle testing to quantify the fatigue performance of several shaped leadless ceramic chip carrier solder joints.