DocumentCode
968487
Title
Exact Path Delay Fault Coverage Calculation of Partitioned Circuits
Author
Kocan, Fatih ; Li, Lun ; Saab, Daniel G.
Author_Institution
Comput. Sci. & Eng. Dept., Southern Methodist Univ., Dallas, TX
Volume
58
Issue
6
fYear
2009
fDate
6/1/2009 12:00:00 AM
Firstpage
858
Lastpage
864
Abstract
Exact path delay fault (PDF) coverage calculation of large circuits with an exponential number of detectable PDFs requires exponential memory space. This often yields memory overflow in computations. One common approach to avoid memory overflow is to partition or virtually cut circuits into several subcircuits and to perform coverage calculation at the partition-level circuit. Partitioning reduces the number of PDFs to be stored in memory exponentially at the expense of losing considerable coverage. This paper describes an algorithm to improve the reported coverage value by recovering the lost PDFs up to a user-controlled degree (Delta), which is a function of the length of cut net sequences. The reported coverage monotonically increases as Delta increases: the exact coverage value is guaranteed when Delta is equal to the number of consecutive partitions on the longest path. Experimental results are provided for the ISCAS85 circuits that illustrate the trade-off between the computation time, the number of partitions, the values of Delta, and the reported coverage. The results indicate that as Delta and the number of partitions increase, the runtime does not increase after some point since the cost of set operations reduces as more partitions are created.
Keywords
delays; integrated circuit testing; ISCAS85 circuits; exact path delay fault coverage calculation; exponential memory space; memory overflow; partition-level circuit; subcircuits; user-controlled degree; Circuit faults; Circuit testing; Clocks; Costs; Data structures; Delay; Electrical fault detection; Fault detection; Integrated circuit modeling; Partitioning algorithms; Runtime; Exact Coverage; Graph Theory; Nonenumerative; Partitioned circuits; Path Delay Fault; Path delay fault; Reliability; Simulation; Test generation; Testing; ZBDD; and Fault-Tolerance; exact coverage; graph theory.; nonenumerative; partitioned circuits;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.2008.205
Filename
4663062
Link To Document