Robust paradigm for diagnosing hold-time faults in scan chains

Hold-time violation is a common cause of failure at scan chains. A robust new paradigm for diagnosing such failures is presented. As compared to previous methods, the main advantage of this is the ability to tolerate non-ideal conditions, for example, under the presence of certain core logic faults or for those faults that manifest themselves intermittently. The diagnosis problem is first formulated as a ´delay insertion process´. Upon this formulation, two algorithms - a ´greedy´ algorithm and a so-called ´best-alignment-based´ algorithm - is proposed. Experimental results on a number of practical designs and ISCAS´89 benchmark circuits are presented to demonstrate its effectiveness.