Phase noise in digital frequency dividers

Author

Levantino, Salvatore ; Romanò, Luca ; Pellerano, Stefano ; Samori, Carlo ; Lacaita, Andrea L.

Author_Institution

Dipt. di Elettronica a Informazione, Politecnico di Milano, Milan, Italy

Volume

39

Issue

5

fYear

2004

fDate

5/1/2004 12:00:00 AM

Firstpage

775

Lastpage

784

Abstract

This paper presents a physical derivation of phase noise in source-coupled-logic frequency dividers. This analysis takes into account both white and flicker noise sources and is verified on two 32/33 dual-modulus prescalers integrated in a 0.35-μm CMOS process. Design techniques for high-speed and low-noise operation are provided. The two integrated prescalers are identical apart from a synchronizing flip-flop at the output of one of them. The measured phase spectra are in good agreement with the estimates and demonstrate that the final synchronization allows a better trade-off between noise and power consumption. The maximum operating frequency is 3 GHz, the power consumption is 27 mW and the phase noise floor is -163 dBc/Hz referred to the 78-MHz output.

Keywords

CMOS logic circuits; digital phase locked loops; flicker noise; flip-flops; frequency dividers; integrated circuit noise; phase noise; power consumption; prescalers; synchronisation; white noise; 0.35 microns; 27 mW; 3 GHz; CMOS process; design techniques; digital frequency dividers; dual-modulus prescalers; flicker noise sources; flip-flop synchronization; high-speed operation; integrated prescalers; low-noise operation; phase noise; phase spectra; physical derivation; source-coupled-logic frequency dividers; white noise sources; 1f noise; CMOS process; Energy consumption; Flip-flops; Frequency conversion; Frequency synchronization; Noise measurement; Phase noise; Power measurement; Process design;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2004.826338

Filename

1291682