DocumentCode
969970
Title
A DC-powered Josephson flip-flop
Author
Hebard, A.F. ; Pei, S.S. ; Dunkleberger, L. ; Fulton, A.F.
Author_Institution
Bell Laboratories, Murray Hill, NJ
Volume
15
Issue
1
fYear
1979
fDate
1/1/1979 12:00:00 AM
Firstpage
408
Lastpage
411
Abstract
A novel dc-powered flip-flop logic and/or memory element utilizing two Josephson tunneling gates has been designed and tested. Circuit resistances R, critical currents Ic , and fanout inductances L are chosen so that the gates operate individually in the latching current-steering mode. However, the gates G1 and G2 are interconnected in such a way that if, say, G1 is at 
and G2 is at V=0, a switching of G2 to returns G1 to the V=0 state. The fanout current redistribution, which accompanies this switching event, occurs with a time constant of about L/R. Switching back to the initial state is a symmetric process. Tolerances on circuit parameter values for proper operation are reasonably wide.
and G2 is at V=0, a switching of G2 to returns G1 to the V=0 state. The fanout current redistribution, which accompanies this switching event, occurs with a time constant of about L/R. Switching back to the initial state is a symmetric process. Tolerances on circuit parameter values for proper operation are reasonably wide.Keywords
Flip-flop memories; Josephson device logic gates; Josephson device memories; Circuit testing; Flip-flops; Inductance; Integrated circuit interconnections; Josephson junctions; Logic design; Logic testing; Switches; Tunneling; Voltage;
fLanguage
English
Journal_Title
Magnetics, IEEE Transactions on
Publisher
ieee
ISSN
0018-9464
Type
jour
DOI
10.1109/TMAG.1979.1060178
Filename
1060178
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