Title :
Low-power gigabit logic by GaAs SSFL
Author :
Hashizume, N. ; Yamada, H. ; Kojima, T. ; Matsumoto, K. ; Tomizawa, K.
Author_Institution :
Electrical Laboratory, Tsukuba, Japan
Abstract :
Experimental results on improved GaAs Schottky-barrier coupled Schottky-barrier gate FET logic (SSFL) are reported. A 13-stage ring oscillator, gate dimensions 1.2×20 ¿m2, showed tpd=55 ps/gate at P=3.5 mW/gate. Also, a divide-by-two circuit was confirmed, starting normal operation from a single initialisation pulse.
Keywords :
III-V semiconductors; Schottky gate field effect transistors; dividing circuits; field effect integrated circuits; gallium arsenide; integrated logic circuits; GaAs Schottky-barrier coupled Schottky-barrier gate FET logic; III-V semiconductor; SSFL; divide-by-two circuit; low power gigabit logic; ring oscillator;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19810387
