• DocumentCode
    972374
  • Title

    A new extraction algorithm for the metallurgical channel length of conventional and LDD MOSFETs

  • Author

    Jean, Yuh-Sheng ; Wu, Ching-Yuan

  • Author_Institution
    Adv. Semicond. Device Res. Lab., Nat. Chiao Tung Univ., Hsinchu, Taiwan
  • Volume
    43
  • Issue
    6
  • fYear
    1996
  • fDate
    6/1/1996 12:00:00 AM
  • Firstpage
    946
  • Lastpage
    953
  • Abstract
    A new extraction algorithm for the metallurgical channel length of conventional and LDD MOSFETs is presented, which is based on the well-known resistance method with a special technique to eliminate the uncertainty of the channel length and to reduce the influence of the parasitic source/drain resistance on threshold-voltage determination. In particular, the metallurgical channel length is determined from a wide range of gate-voltage-dependent effective channel lengths at an adequate gate overdrive. The 2-D numerical analysis clearly show that adequate gate overdrive is strongly dependent on the dopant concentration in the source/drain region. Therefore, an analytic equation is derived to determine the adequate gate overdrive for various source/drain and channel doping. It shows that higher and lower gate overdrives are needed to accurately determine the metallurgical channel length of conventional and LDD MOSFET devices, respectively. It is the first time that we can give a correct gate overdrive to extract Lmet not only for conventional devices but also for LDD MOS devices. Besides, the parasitic source/drain resistance can also be extracted using our new extraction algorithm
  • Keywords
    MOSFET; electric resistance measurement; length measurement; semiconductor device models; 2-D numerical analysis; LDD MOSFET; adequate gate overdrive; analytical model; dopant concentration; extraction algorithm; gate-voltage-dependent effective channel lengths; metallurgical channel length; parasitic source/drain resistance; resistance method; threshold-voltage determination; Algorithm design and analysis; Capacitance measurement; Doping; Electrical resistance measurement; Equations; MOSFET circuits; Numerical analysis; Parasitic capacitance; Performance analysis; Uncertainty;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/16.502128
  • Filename
    502128