Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI´s

Author

Horiguchi, Masashi ; Sakata, Takeshi ; Itoh, Kiyoo

Author_Institution

Central Res. Labs., Hitachi Ltd., Tokyo, Japan

Volume

28

Issue

11

fYear

1993

fDate

11/1/1993 12:00:00 AM

Firstpage

1131

Lastpage

1135

Abstract

A switched-source-impedance (SSI) CMOS circuit is proposed as a means of reducing the exponential increase of subthreshold current with threshold-voltage scaling. Inserting a switched impedance at the source of a MOS transistor reduces the standby subthreshold current of giga-scale LSI´s operating at room temperature by three to four orders of magnitude and suppresses the current variation caused by threshold-voltage and temperature fluctuations. The scheme is applicable to any combinational and sequential CMOS logic circuits as long as their standby node voltages are predictable. The standby current of a 16-Gb DRAM is expected to be reduced from 1.1 A to 0.29 mA using this scheme. Hence, battery backup of giga-scale LSI´s will be possible even at room temperature and above

Keywords

CMOS integrated circuits; combinatorial circuits; integrated logic circuits; integrated memory circuits; large scale integration; sequential circuits; 0.29 mA; 16 Gbit; CMOS circuit; DRAM; MOS transistor; battery backup; combinational circuits; giga-scale LSI; logic circuits; low standby subthreshold current; room temperature; sequential circuits; standby node voltages; switched impedance; switched-source-impedance; threshold-voltage scaling; Batteries; CMOS logic circuits; Fluctuations; Impedance; MOSFETs; Random access memory; Subthreshold current; Switching circuits; Temperature; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.245593

Filename

245593