Performance of a scaled Si gate n-well CMOS technology

A scaled n-well CMOS technology with 40 nm gate oxide, 1 ¿m PMOS and 2 ¿m NMOS transistors has been realised with peak effective mobilities of 710 and 260 cm2V¿1s¿1 for electrons and holes, respectively, and available voltage gains as high as 80 for a 1 ¿m PMOS and 115 for a 2 ¿m NMOS transistor. The corresponding maximum inverter gain was 75. The inverter supply voltage range was 1.5 to 12 V and the inverter delay time was 300 ps at 5 V supply voltage.