Statistical techniques for the computer-aided optimization of analog integrated circuit

A CAD tool capable of performing statistical circuit simulation, design, and optimization is described. The core of this tool is a general, CAD-compatible, statistical model which accounts for the effect of device area, transistor bias, and circuit layout on the variation of MOS integrated circuits. The statistical model has been incorporated into an object-oriented circuit simulator, APLAC, which has sufficient flexibility to allow optimization loops within a simulation input deck. The optimization of a two-stage operational amplifier, including the optimization of the standard deviation of the offset voltage, is performed using both steepest descent and constrained optimization techniques as an illustration of this statistical CAD tool. In this example, it is shown that the transistors which cause variations in op-amp circuit performance can be identified and resized in an area-efficient manner to meet a prescribed parametric circuit yield.