Title :
40-Gb/s High-Gain Distributed Amplifiers With Cascaded Gain Stages in 0.18-μm CMOS
Author :
Chien, Jun-Chau ; Lu, Liang-Hung
Author_Institution :
Nat. Taiwan Univ., Taipei
Abstract :
A novel circuit topology for high-gain distributed amplifiers is presented in this study. Based on the conventional distributed architecture, the gain cells are realized by cascading cas- code stages for gain enhancement. In addition, the stagger-tuning technique is extensively utilized in the design of the cascode stages as well as the cascaded stages, leading to significant improvement in terms of the operating bandwidth and the gain flatness. With the proposed circuit architecture, two amplifiers are implemented in a standard 0.18-mum CMOS technology. The amplifier with a 3 times 3 configuration exhibits a gain of 16.2 dB and a 3-dB bandwidth of 33.4 GHz, while the one in a form of 2 times 4 demonstrates a gain of 20 dB and a bandwidth of 39.4 GHz. Consuming a dc power of 260 mW from a 2.8-V supply voltage, both circuits provide clear eye-opening with a pseudorandom bit sequence (PRBS) at 40 Gb/s.
Keywords :
CMOS integrated circuits; cascade networks; circuit tuning; distributed amplifiers; millimetre wave amplifiers; network topology; CMOS technology; cascaded gain stages; circuit architecture; circuit topology; frequency 39.4 GHz; high-gain distributed amplifiers; pseudorandom bit sequence; stagger-tuning technique; Bandwidth; Broadband amplifiers; CMOS technology; Circuits; Distributed amplifiers; Gain; Impedance; Low-noise amplifiers; Propagation losses; Transmission lines; Bandwidth enhancement; distributed amplifiers; gain flatness; gain–bandwidth product; inductive peaking; stagger-tuning technique;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2007.908688
