• DocumentCode
    974199
  • Title

    Speed-power property of GaAs Schottky-barrier coupled Schottky-barrier gate FET logic

  • Author

    Tomizawa, Keiichi ; Hashizume, Nobuya ; Matsumoto, Kaname ; Suzuki, F.

  • Author_Institution
    Electrotechnical Laboratory, Tsukuba, Japan
  • Volume
    17
  • Issue
    21
  • fYear
    1981
  • Firstpage
    821
  • Lastpage
    822
  • Abstract
    Results from computer simulation of a GaAs Schottky-barrier coupled Schottky-barrier gate FET logic inverter of different values of Vp are reported. It is shown that the inverter of gate dimensions 1 × 10 ¿m¿2, Vp = ¿1 V, and fan-out of one has tpd = 17 ps and P = 1 mW, and that still lower power consumption is possible with smaller |Vp|. Problems associated with small |Vp| are also discussed.
  • Keywords
    III-V semiconductors; Schottky effect; Schottky gate field effect transistors; field effect integrated circuits; gallium arsenide; integrated logic circuits; GaAs Schottky-barrier coupled Schottky-barrier gate FET logic inverter; computer simulation; small pulse voltage magnitude; speed-power property;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19810572
  • Filename
    4246052
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=974199