Analysis of Options in Double-Gate MOS Technology: A Circuit Perspective

Author

Cakici, Riza Tamer ; Roy, Kaushik

Author_Institution

Texas Instrum., Dallas

Volume

54

Issue

12

fYear

2007

Firstpage

3361

Lastpage

3368

Abstract

Double-gate MOS (DGMOS) technologies are emerging as possible substitutes for single-gate planar bulk devices in the near future. This paper defines and presents different DGMOS device-and circuit-design possibilities. It studies Schmitt triggers to eloquently analyze the interplay between noise immunity, circuit speed, and power dissipation as a function of device-level parameters. The asymmetric DGMOS devices and independent-gate technology can provide high noise immunity and dynamic power reduction at increased gate-delay, leakage-power, and process-sensitivity penalties. Furthermore, connected-gate DGMOS circuits work best with symmetric devices.

Keywords

MIS devices; MOS integrated circuits; trigger circuits; Schmitt triggers; asymmetric DGMOS devices; connected-gate DGMOS circuits; double-gate MOS technology; dynamic power reduction; independent-gate technology; noise immunity; single-gate planar bulk devices; Circuit noise; Costs; Electrostatics; Immune system; Instruments; Logic devices; Noise reduction; Power dissipation; Semiconductor device noise; Trigger circuits; Asymmetric double-gate MOS (DGMOS); DGMOSFETs; Schmitt trigger; independent-gate technology; symmetric DGMOS;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2007.909057

Filename

4383015