An analog implementation of discrete-time cellular neural networks

Author

Harrer, Hubert ; Nossek, Josef A. ; Stelzl, Rudolf

Author_Institution

Tech. Univ. of Munich, Germany

Volume

3

Issue

3

fYear

1992

fDate

5/1/1992 12:00:00 AM

Firstpage

466

Lastpage

476

Abstract

An analog circuit structure for the realization of discrete-time cellular neural networks (DTCNNs) is introduced. The computation is done by a balanced clocked circuit based on the idea of conductance multipliers and operational transconductance amplifiers. The circuit is proposed for a one-neighborhood on a hexagonal grid, but can also be modified to larger neighborhoods and/or other grid topologies. A layout was designed for a standard CMOS process, and the corresponding HSPICE simulation results are given. A test chip containing 16 cells was fabricated, and measurements of the transfer characteristics are provided. The functional behavior is demonstrated for a simple example

Keywords

CMOS integrated circuits; analogue circuits; digital simulation; neural nets; HSPICE simulation results; analog circuit structure; balanced clocked circuit; conductance multipliers; discrete-time cellular neural networks; grid topologies; hexagonal grid; layout; operational transconductance amplifiers; transfer characteristics; Analog circuits; CMOS process; Cellular neural networks; Circuit simulation; Circuit testing; Circuit topology; Clocks; Network topology; Operational amplifiers; Transconductance;

fLanguage

English

Journal_Title

Neural Networks, IEEE Transactions on

Publisher

ieee

ISSN

1045-9227

Type

jour

DOI

10.1109/72.129419

Filename

129419