Effects of oxide interface traps and transient enhanced diffusion on the process modeling of PMOS devices

We present a model which simulates the trapping of arsenic and boron dopants at the silicon-silicon dioxide interface, and demonstrate that this model gives significantly more accurate doping profiles for a wide range of PMOS devices, as characterized by the device Threshold Voltage. In addition, a newly-developed Transient Enhanced Diffusion (TED) model is applied for the first time to the process simulation of buried-channel PMOS devices, predicting an enhanced Short Channel Effect and Drain Induced Barrier Lowering (DIBL) effect. By using both these models, an excellent agreement is achieved between simulated and measured device characteristics for PMOS devices with gate lengths varying from 2 to 0.4 μm, over a wide range of bias conditions and operating temperatures