• DocumentCode
    976165
  • Title

    Decoded-source sense amplifier for high-density DRAMs

  • Author

    Okamura, Jun-ichi ; Okada, Yoshio ; Koyanagi, Masaru ; Takeuchi, Yoshiaki ; Yamada, Minoru ; Sakurai, Kiyofumi ; Imada, Sadao ; Saito, Shozo

  • Author_Institution
    Toshiba Corp., Kawasaki, Japan
  • Volume
    25
  • Issue
    1
  • fYear
    1990
  • fDate
    2/1/1990 12:00:00 AM
  • Firstpage
    18
  • Lastpage
    23
  • Abstract
    The decoded-source sense amplifier (DSSA) for high-speed, high-density DRAMs is discussed. To prevent clamping of the common-source node of the sense amplifier caused by bit-line discharge current, the DSSA has an additional latching transistor with a gate controlled by a column decoder. The DSSA has been successfully installed in a 4-Mb DRAM and provided a RAS access time of 60 ns under a Vcc of 4 V at 85°C
  • Keywords
    CMOS integrated circuits; VLSI; amplifiers; integrated circuit technology; integrated memory circuits; random-access storage; 4 Mbit; 4 V; 60 ns; 85 C; DSSA; ULSI; access time; additional latching transistor; column decoder; decoded-source sense amplifier; high-density DRAMs; high-speed; Aluminum; Capacitance; Clamps; Decision support systems; Decoding; Operational amplifiers; Random access memory; Storage area networks; Voltage; Wiring;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/4.50278
  • Filename
    50278
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=976165