Title :
The stabilized reference-line (SRL) technique for scaled DRAMs
Author :
Tsuchida, Kenji ; Oowaki, Yukihito ; Ohta, Masako ; Takashima, Daisaburo ; Watanabe, Shigeyoshi ; Ohuchi, Kazunori ; Masuoka, Fujio
Author_Institution :
Toshiba Corp., Kawasaki, Japan
fDate :
2/1/1990 12:00:00 AM
Abstract :
The stabilized reference-line (SRL) technique, which reduces bit-line interference noise, is described. This technique can eliminate the capacitance coupling noise generated when the cell data are transferred to the bit line. As a result, the noise generated by the sensing timing difference, which is caused by the coupling noise, does not arise. Furthermore, the SRL technique can be realized by modifying the conventional folded bit-line architecture. Therefore, it is easy to apply the SRL technique to high-density DRAMs
Keywords :
MOS integrated circuits; VLSI; integrated circuit technology; integrated memory circuits; random-access storage; ULSI; bit line interference noise; capacitance coupling noise elimination; folded bit-line architecture; high-density DRAMs; multi megabit memories; reduces bit-line interference noise; scaling; stabilised reference line technique; Associate members; Capacitance; Degradation; Interference; Noise generators; Noise reduction; Random access memory; Testing; Timing; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
