A latch-up-like new failure mechanism for high-density CMOS dynamic RAMs

Author

Furuyama, Tohru ; Ishiuchi, Hidemi ; Tanaka, Hiroto ; Watanabe, Yohji ; Kohyama, Yusuke ; Kimura, Tohru ; Muraoka, Kazuyoshi ; Sugiura, Souichi ; Natori, Kenji

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

25

Issue

1

fYear

1990

fDate

2/1/1990 12:00:00 AM

Firstpage

42

Lastpage

47

Abstract

A latch-up-like failure phenomenon that shows hysteresis in the V_cc-I_cc characteristics observed in a high-density CMOS dynamic RAM that utilizes an on-chip substrate-bias generator is discussed. This failure is caused by large substrate-current generation due to the depletion-mode threshold voltage of n-channel transistors at near-zero substrate-bias operation. It is increasingly important not only to design a powerful substrate-bias generator but also to suppress the back-gate bias effect on the n-channel transistor

Keywords

CMOS integrated circuits; VLSI; failure analysis; integrated circuit technology; integrated memory circuits; random-access storage; ULSI; V-I characteristic hysteresis; back-gate bias effect suppression; depletion-mode threshold voltage; failure mechanism; high density CMOS DRAM; large substrate-current generation; latch-up-like failure phenomenon; multi megabit memories; n-channel transistors; near-zero substrate-bias operation; on-chip substrate-bias generator; Character generation; DRAM chips; Failure analysis; Hysteresis; Power engineering and energy; Power generation; Random access memory; Read-write memory; Transistors; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.50282

Filename

50282