A 3.8-ns 16 K BiCMOS SRAM

Author

Heimsch, Wolfgang ; Krebs, Roland ; Pfaffel, Bruno ; Ziemann, Klaus

Author_Institution

Siemens AG, Munich, West Germany

Volume

25

Issue

1

fYear

1990

fDate

2/1/1990 12:00:00 AM

Firstpage

48

Lastpage

54

Abstract

A 2 K×8-b, ECL 100 K compatible BiCMOS SRAM with 3.8-ns (-4.5 V, 60°) address access time is described. The precisely controlled bit-line voltage swing (60 mV), a current sensing method, and optimized ECL decoding circuits permit a reliable and fast readout operation. The SRAM features an on-chip write pulse generator, latches for input and output bits, and a full six-transistor CMOS cell array. Power dissipation is approximately 2 W, and the chip size is 3.9×5.9 mm². The SRAM was based on 1.2-μm BiCMOS, using double-metal, triple-polysilicon, and self-aligned bipolar transistors

Keywords

BIMOS integrated circuits; VLSI; integrated circuit technology; integrated memory circuits; random-access storage; 1.2 micron; 16 kbit; 2 W; 2 kbyte; 3.8 ns; 3.9 to 5.9 mm; BiCMOS SRAM; ECL 100 K compatible; VLSI; address access time; chip size; controlled bit-line voltage swing; current sensing method; double-metal; fast readout operation; features; latches; on-chip write pulse generator; optimized ECL decoding circuits; power dissipation; self-aligned bipolar transistors; six-transistor CMOS cell array; triple-polysilicon; BiCMOS integrated circuits; Clocks; Driver circuits; Energy consumption; Power dissipation; Pulse generation; Random access memory; Signal generators; Space vector pulse width modulation; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.50283

Filename

50283