An α-immune, 2-V supply voltage SRAM using a polysilicon PMOS load cell

Author

Ishibashi, Koichiro ; Yamanaka, Toshiaki ; Shimohigashi, Katsuhiro

Author_Institution

Hitachi Ltd., Tokyo, Japan

Volume

25

Issue

1

fYear

1990

fDate

2/1/1990 12:00:00 AM

Firstpage

55

Lastpage

60

Abstract

The key technology for achieving the low-voltage operation is shown to be a polysilicon PMOS load (PPL) cell. The polysilicon PMOS device is successfully stacked on the bulk MOSFET, using 0.5-μm CMOS technology. The investigation emphasizes the soft error rate (SER) and the stability of the cell. The SER of the PPL cell at a supply voltage of 2 V is comparable to that of the conventional high-resistivity polysilicon load cell at a supply voltage of 5 V. The cell stability is also improved using a PPL cell, so that the low-voltage operation is assured

Keywords

CMOS integrated circuits; VLSI; integrated circuit technology; integrated memory circuits; random-access storage; 0.5 micron; 2 V; CMOS; PPL cell; SER; SRAM; VLSI; alpha particle immune RAM; bulk MOSFET; cell stability; key technology; low-voltage operation; polycrystalline Si; polysilicon PMOS load cell; soft error rate; submicron; supply voltage; CMOS technology; Capacitors; Electrodes; Error analysis; Low voltage; MOS devices; MOSFET circuits; Power MOSFET; Random access memory; Stability;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.50284

Filename

50284