• DocumentCode
    976592
  • Title

    Heuristic algorithm for low power design of combinational circuits

  • Author

    Kim, H. ; Hwang, S.-Y.

  • Author_Institution
    Dept. of Electron. Eng., Sogang Univ., Seoul, South Korea
  • Volume
    32
  • Issue
    12
  • fYear
    1996
  • fDate
    6/6/1996 12:00:00 AM
  • Firstpage
    1066
  • Lastpage
    1067
  • Abstract
    A heuristic algorithm is proposed for the low power implementation of combinational circuits. By observing the structure of a given function, the proposed algorithm selects an input variable of a given function and performs Shannon expansion with respect to the variable to reduce the number of gates in the subcircuit realising the function. Experimental results show the efficiency of the proposed algorithm
  • Keywords
    circuit CAD; combinational circuits; integrated circuit design; logic CAD; Shannon expansion; combinational circuits; heuristic algorithm; input variable selection; low power design;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19960701
  • Filename
    502854
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=976592