An on-chip smart memory for a data-flow CPU

Author

Uvieghara, Gregory A. ; Nakagome, Yoshinobu ; Jeong, Deog-Kyoon ; Hodges, David A.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Volume

25

Issue

1

fYear

1990

fDate

2/1/1990 12:00:00 AM

Firstpage

84

Lastpage

94

Abstract

Register Alias Table (RAT) is a smart memory that is embedded in HPSm (High-Performance Substrate), a Berkeley data-flow CPU. It is a multiport memory that has content addressability and support for branch prediction and exception handling, in addition to conventional read and write operations. An experimental 1240-b smart memory chip is implemented in a 1.6-μm double-metal scalable CMOS process. This memory performs 15 operations within a cycle time of 100 ns, has 34658 transistors, occupies an area of 3.8 mm×5.2 mm, and dissipates 0.51 W

Keywords

CMOS integrated circuits; VLSI; content-addressable storage; integrated memory circuits; random-access storage; 0.51 W; 1.6 micron; 100 ns; 1240 bit; 3.8 to 5.2 mm; Berkeley data-flow CPU; HPSm; High-Performance Substrate; RAT; Register Alias Table; VLSI; branch prediction; chip area; content addressability; cycle time; data-flow CPU; double-metal scalable CMOS process; exception handling; multiport memory; on-chip smart memory; power dissipation; read operations; smart memory chip; write operations; CMOS process; Centralized control; Helium; Laboratories; Logic; Out of order; Random access memory; Read-write memory; Registers; Transistors;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.50289

Filename

50289