A review of fault-tolerant techniques for the enhancement of integrated circuit yield

This paper examines the ways in which the yield of integrated circuit production can be improved through the use of circuit design techniques. The bulk of the paper is concerned with fault-tolerant approaches but aspects of circuit layout are also considered briefly. The paper reviews the fault-tolerant techniques which are currently in use in memory chips and discusses those which have been proposed for other architectures and large-area chips up to whole wafers. It surveys the crucial topics of yield prediction and of repair technology and outlines the options available for the future.