Title :
Area-efficient high-speed carry chain
Author_Institution :
Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran
Abstract :
An improved carry chain circuit with carry-skip capability is described. The carry-skip logic allows an arbitrarily long carry chain without the need for intermediate buffers for signal restoration, leading to an implementation that is both fast and area-efficient. The chain can flexibly accommodate technology-imposed maximum depth of NMOS transistor pull-down stack.
Keywords :
adders; carry logic; NMOS transistor pull-down stack; arbitrarily long carry chain; area-efficient high-speed carry chain; carry-skip capability; carry-skip logic; improved carry chain circuit; signal restoration; technology-imposed maximum depth;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20071613
