An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS

This paper presents a network-on-chip (NoC) SerDes transceiver architecture for long distance interconnects in the mm range within MPSoCs. Its source synchronous clocking scheme enables application in GALS systems and allows completely stoppable transceiver clocking for low idle power consumption. A capacitive line driver with combined resistive driver for well defined DC swing is employed and analyzed in detail by simulation studies. It is shown that proper DC swing definition is mandatory for robust operation of long links at high data rates. Prototypes of the transceiver over 6 mm bufferless on-chip interconnect are implemented in both 65 nm and 28 nm CMOS technologies. The 65 nm realization achieves an efficiency of 173 fJ/bit/mm at 90 Gbit/s at 1.25 V and 93 fJ/bit/mm at 45 Gbit/s low speed mode at 0.9 V. The 28 nm realization achieves 81 fJ/bit/mm at 72 Gbit/s at 1.05 V and 64 fJ/bit/mm at 36 Gbit/s low speed mode at 0.95 V. The transceiver can be seamlessly integrated as black box point-to-point connection into heterogeneous MPSoC NoCs to enable ultra-compact toplevel floorplan realization and increased energy efficiency. An example of a 20-core MPSoC in 65 nm CMOS technology with 10 serial NoC transceivers is presented.