• DocumentCode
    980472
  • Title

    Synthesis of multilevel multiplexer circuits for incompletely specified multioutput Boolean functions with mapping to multiplexer based FPGA´s

  • Author

    Schäfer, Ingo ; Perkowski, Marek A.

  • Author_Institution
    Lattice Semicond. Corp., Santa Clara, CA, USA
  • Volume
    12
  • Issue
    11
  • fYear
    1993
  • fDate
    11/1/1993 12:00:00 AM
  • Firstpage
    1655
  • Lastpage
    1664
  • Abstract
    The introduction of the multiplexer-based Actel FPGA series ACT resulted in an increased interest in multiplexer circuits. This paper introduces a level-by-level top-down minimization algorithm for them. The concept of a local transform is applied for the generalization of the ratio parameter method for M(1) multiplexer synthesis having one data select input and a spectral method for M(2) multiplexer synthesis to determine redundant multiplexer inputs for M(k) multiplexer circuits. The algorithm developed for multilevel synthesis of M(k) multiplexer circuits for incompletely specified multioutput Boolean functions takes advantage of the combination of spectral and Boolean methods. The obtained multiplexer circuit can be directly realized with FPGA´s like the Actel ACT series or the CLi 6000 series from Concurrent Logic. A simple heuristic is applied to map an M(1) multiplexer circuit to the Actel ACT1 family
  • Keywords
    Boolean functions; circuit CAD; logic CAD; logic arrays; minimisation of switching nets; multiplexing equipment; Actel FPGA series ACT; CLi 6000 series; Concurrent Logic; incompletely specified functions; local transform; multilevel multiplexer circuits; multilevel synthesis; multioutput Boolean functions; multiplexer based FPGA; ratio parameter method; spectral method; top-down minimization algorithm; Boolean functions; Circuit synthesis; Field programmable gate arrays; Input variables; Linearity; Logic functions; Minimization methods; Multiplexing; Network synthesis; Utility programs;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.248076
  • Filename
    248076