Title :
Optimal folding of bit sliced stacks
Author :
Paik, Doowon ; Sahni, Sartaj
Author_Institution :
AT&T Bell Labs., Murray Hill, NJ, USA
fDate :
11/1/1993 12:00:00 AM
Abstract :
We develop polynomial time algorithms to optimally fold stacked bit sliced architectures to minimize area subject to height or width constraints. These algorithms may also be applied to folding problems that arise in standard cell and sea-of-gates designs
Keywords :
circuit layout CAD; logic CAD; network routing; CAD; SOG design; bit sliced architectures; bit sliced stacks; height constraints; polynomial time algorithms; sea-of-gates designs; standard cell; width constraints; Algorithm design and analysis; CMOS technology; Circuits; Design optimization; Polynomials; Routing; Space technology; Wires;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
