Title :
An efficient algorithm for VLSI network partitioning problem using a cost function with balancing factor
Author :
Park, Chan-Ik ; Park, Yun-Bo
Author_Institution :
Dept. of Comput. Sci., Pohang Inst. of Sci. & Technol., South Korea
fDate :
11/1/1993 12:00:00 AM
Abstract :
This paper presents an efficient algorithm for network partitioning problem, which improves Fiduccia and Mattheyses´ (F-M´s) algorithm (1982). We have noticed that the main problem of F-M´s algorithm is that the cell move operation is largely influenced by the balancing constraint. In order to handle this kind of inherent limitation in F-M´s algorithm, a cost function is adopted which reflects balance degree of a partition as well as its cutset size. The weighting factor R is introduced in the cost function to determine the relative importance of the two factors: cutset size and balance degree. Using this cost function, we propose an iterative improvement algorithm which has the time complexity of O(b(m+c2)), where b is the number of blocks, m is the size of network, and c is the number of cells. It is proven that the proposed algorithm guarantees to find a balanced partition if the value of R satisfies a certain condition. Experimental results show that the proposed algorithm outperforms F-M´s algorithm in most cases
Keywords :
VLSI; circuit layout CAD; computational complexity; integrated circuit technology; VLSI network partitioning problem; balance degree; balanced partition; balancing factor; cell move operation; cost function; cutset size; iterative improvement algorithm; weighting factor; Computer science; Cost function; Design automation; Heuristic algorithms; Integrated circuit interconnections; Iterative algorithms; Partitioning algorithms; Polynomials; Very large scale integration;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on