Analysis and characterization of device variations in an LSI chip using an integrated device matrix array

For future large-scale integration design technology, the device matrix array (DMA), which precisely evaluates within-die variation in device parameters, has been developed. The DMA consists of a 14-by-14 array of common units. The unit size is 240 by 240 μm, and each unit contains 148 measurement elements (52 transistors, 30 capacitors, 51 resistors, and 15 ring oscillators). The element selection and precise measurement are achieved with low parasitic resistance measurement buses and leakage-controlled switching circuits, which allow the measurement accuracy for a transistor, resistor, or capacitor of 90 pA, 11 mΩ, and 23 aF, respectively, in the 3σ range. The ability to obtain 29 008 samples from a chip enables statistical analysis of the variation in 148 elements of each chip with 240-μm spatial resolution. This high resolution and large sample number allows us to precisely decompose the data into systematic and random variation parts with newly developed fourth-order polynomial fitting. Our methodology has been verified using a test chip fabricated by a 130-nm CMOS process with a 100-nm physical gate length and five Cu interconnect layers. In MOSFETs, the random part was dominant and indicated a certain σ value in every chip. In the case of the interconnect layers, the random and systematic parts of the resistance and the capacitance indicated variance fluctuations. By chip, by item, by size, by structure, random or systematic, the σ values of each variation show inconsistency which we believe is attributable to the Cu process. The correlation coefficients of systematic part between device element and ring oscillator frequency shown very high value (0.87-0.98), and those of a random part were low enough (-0.10-0.22) to prove the accuracy of decomposition.